| 摘要 |
<p>A d.c. blocking amplifier circuit which has a fast start-up time and can be d.c. coupled to other similar circuits or cascaded with differential amplifiers. The circuit is suitable for use in digital paging receivers which operate a battery economising regime. The circuit comprises first and second differential amplifiers (40,42 and 44,46) and first and second balanced input lines (52,56), the first input line (52) being connected to the first differential amplifier which in operation amplifies an a.c. signal applied by way of the first input line (52), and the second input line (56) being connected to the second differential amplifier (44,46) which in operation amplifies an a.c. signal applied by way of the second input line (56). Outputs of the first and second differential amplifiers (40,42 and 44,46) are combined to produce an amplified signal which is independent of the d.c. conditions on each of the first and second balanced signal input lines.</p> |
