| 摘要 |
PURPOSE:To prevent a conventionally generated phase difference and to prevent the occurrence of glitch noise by inputting the clock signal, which is supplied to a 6-bit shift register, to a synchronous counter operated as a shift register. CONSTITUTION:Inputted data is successively inputted to a 6-bit shift register 1, and the output of the 6-bit shift register 1 at each moment is decoded by a decoder 2A. When five bits of 6-bit data are logical '1' continuously and the next bit is logical '0', the decoder 2A generates the output of logical '1', and loading is not indicated to 4-bit synchronous counters 6 and 7. Consequently, preset data is not preset though a clock signal is inputted, and data of preset data terminals D2 to D4 of the counter 6 and preset data terminals D1 to D5 and an output terminal Q4 of the counter 7 are not changed and preceding values are held there, and thus, zero deletion is performed. |
