Semiconductor memory cells and semiconductor memory device employing the semiconductor memory cells

摘要

A spare memory cell (1) comprises a read FET (3) (Field Effect Transistor), a fusing FET (5) and a current fuse (7). The FETs (3, 5) are connected in series between a read data line (13) and a low voltage source (15). The fuse (7) is inserted between a series node of the FETs and a write data line (17). The fuse (7) is molten when data is written to the spare memory cell (1). By applying a power source voltage to a control electrode of the fusing FET and by applying a voltage that is higher than the power source voltage to the write data line (17), the fusing FET (3) is set to its secondary breakdown state. Under this state, a large current flows through the fusing FET (3) to cut off the fuse (7), thus writing data to the spare memory cell (1).