| 摘要 |
PURPOSE:To improve the reliability of transmission by making the interval of synchronization of a received data narrow. CONSTITUTION:After a received data is inputted to a flip-flop 1, its output is fed to an input of a flip-flop 2 and the flip-flop processing from one output to other input is repeated for 8 times corresponding to a bit number of a data afterward. Through the processing above, the leading and trailing of the received data are detected through the processing. Then an OR output from the flip-flops 1, 2 connects to a preset input via NAMD gates 6, 7 and an ANB gate 8, sampling is applied by a 32MHz clock at the receiver side to generate a synchronization clock in 4MHz with respect to the received data. The clock is inputted to a CMI modulator 4 to read the received data outputted from the flip-flop 2. |
