| 摘要 |
PURPOSE:To improve the integration of a semiconductor memory device by omitting a drain region of a switching MISFET, thereby reducing the area of a memory cell. CONSTITUTION:A memory cell is obtained from a bit line, a word line 6, an electrode 3' of a capacitance element made of polycrystalline silicon, a gate electrode 5 of a switching MISFET made of a polycrystalline silicon layer formed on an insulating film 2' overlapped with the bit line and the capacitance element through an insulating film 3'' and a source region 4 made of p<+> type region. In this case the line 6 crosses the polycrystalline silicon layer to become a gate electrode, and is formed of an aluminum wiring layer connected via connecting points C1, C2 to the gae electrode. In this manner, the cell area can be reduced. |
