发明名称 METHOD OF PULLING-IN PLL FREQUENCY SYNTHESIZER
摘要 PURPOSE:To make a PLL frequency synthesizer compact by composing a circuit which forcibly makes PLL in-phase of a digital circuit suitable for LSI. CONSTITUTION:The PLL frequency synthesizer is composed of a phase comparator 2, loop filter 3, voltage controlled oscillator 4 and variable frequency divider 5 and to these parts, a synchronization detector 6 and a frequency dividing ratio control circuit 8 are added for the PLL to forcibly make the PLL in-phase at the time of being in non in-phase state. The circuit for this PLL to forcibly make the PLL the in-phase state at the time of being in non in-phase state can be composed of the digital circuit suitable for LSI. Thus, the PLL frequency synthesizer can be made compact.
申请公布号 JPH02272914(A) 申请公布日期 1990.11.07
申请号 JP19890092881 申请日期 1989.04.14
申请人 HITACHI LTD;HITACHI COMMUN SYST INC 发明人 SUZUKI MASASHIGE
分类号 H03L7/12 主分类号 H03L7/12
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