| 摘要 |
<p>PURPOSE:To alternately output an input clock flag and a device clock flag even if the phase of an input clock is shifted by installing an output sequence control means and controlling the operation of a gate means. CONSTITUTION:An input clock flag generation means 2 and a device clock flag generation means 3 generate a synchronous input clock synchronized with a sequential clock and a synchronous device clock. They generate the input clock flag and the device clock flag whenever the prescribed change points (rise point, for example) of two kinds of clocks are detected, and transmit them to the gate means 5. When the output sequence control means 4 detects that the input clock flag has been outputted, it transmits a gate control signal to output the device clock flag. Even if the input clock is inputted prior to the device clock owing to jitter, a passage is prevented by the gate means 5, and the device clock flag is transmitted from the gate means 5. Thus, the input clock flag and the device clock flag are alternately outputted even if the phase of the input clock is shifted.</p> |
