发明名称 DATA TRANSFER SYSTEM FOR MULTIPROCESSOR DEVICE
摘要 PURPOSE:To make the data transfer between CPU units possible without paying attention to the control state of the CPU of the data transfer destination, by using a main storage device as a medium and controlling properly a common bus. CONSTITUTION:A main storage device 13 is used as a medium through a common bus 15 for the data transfer among CPU units 12-0-12-N. When the CPU unit 12-1 requests the data transfer to the CPU unit 12-0, the unit 12-1 uses the bus 15 to transfer data. The unit 12-0 monitors always the device 13 and accesses the device 13 at its convenience when the bus 15 is idle, and data transferred from the unit 12-1 is taken into the unit 12-0.
申请公布号 JPS57211660(A) 申请公布日期 1982.12.25
申请号 JP19810095402 申请日期 1981.06.22
申请人 ANRITSU DENKI KK 发明人 ITAYA HIROSHI;NAKATSUGAWA KENJI
分类号 G06F15/16;G06F12/00;G06F13/38;G06F15/167;G06F15/177 主分类号 G06F15/16
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