| 摘要 |
PURPOSE:To control the phase of a motor finely by accumulating reference clocks through a first counter and accumulating the frequency of speed signal of the motor through a second counter then carrying out subtraction of the accumulated values. CONSTITUTION:A first counter 4 accumulates reference clocks having same frequency as that of a speed signal FG to be outputted from a frequency generator when the motor 1 rotates with a regular rotary speed. The accumulated value (d) is outputted with same period as the reference clock and the accumulated value is reset every time when a playback control signal PBCTL is received. A second counter 5 receives a speed signal FG from the frequency generator and outputs an accumulated value (c) with same period as the reference clock. The second counter 5 also receives the playback control signal PBCTL and resets the accumulated value (c). On the other band, a subtractor 6 calculates the difference (e) between the accumulated value (d) in the first counter 4 and the accumulated value (c) in the second counter 5, then the difference (e) is fed to a D/A converter 7. |
