Charge coupled shift memory - alternating clock signals to allow increased storage density

摘要

An SPS type charge shift memory of increased storage density, with a series of alternating first and second type elements each associated with a parallel circuit of elements to take the charges representing the input data from the writing wires, and with a series of alternating read-out elements fed from the parallel circuits. The first type charge displacement elements of the writing chain and the reading chain are drived by a first clock at a higher frequency and the second type elements at the same frequency with a phase shift. Between the charge displacement elements of the writing chain and of the reading there are transfere electrodes which take up data when driven at clock rates.