| 摘要 |
PURPOSE:To decrease the circuit scale by squaring a sampled input signal, generating a difference signal between the squared signal and a signal resulting from retarding the squared signal by a half period of the timing component and accumulating the difference signal and outputting it. CONSTITUTION:An input signal is sampled in the timing of a clock signal and the result is fed to a multiplier 1. The multiplier 1 squares an input signal and gives the result to one input terminal of a subtractor 3, the signal is retarded by a half the clock period T of the input signal at a delay device 2 and given to the other input terminal of the subtractor 3. A difference signal sent from the subtractor 3 is sampled at an interval of the clock period T of the input signal to a switch SW2 and fed to an adder 4. A multiplier 5 multiplies a constant (a) smaller than 1 with a transmission signal from the adder 4, which adds and outputs the signal resulting from the input signal retarded by the period T of the clock at a delay device 6 to the signal from the switch SW2. Thus, the increase and divergence of the result of accumulation is prevented. |
