发明名称 VIDEO SIGNAL PROCESSING APPARATUS
摘要 The apparatus comprises a delay circuit (3) for delaying an input signal by a predetermined time. An operational circuit (4) conducts an addition or substraction operation between an output signal of the delay circuit and an input video signal. A nonlinear processing circuit (9) receives an output signal of the operational circuit (4) and generates two output signals. One output signal has a gain that decreases with an increase of the absolute value of the level of the output signal and becomes zero when the absolute value exceeds a specified value. A further operational circuit (2) conducts an addition or subtraction operation between the output signal of the nonlinear processor (9) and the input video signal. The operation result is output to the delay circuit (3).
申请公布号 KR900008236(B1) 申请公布日期 1990.11.06
申请号 KR19860002487 申请日期 1986.04.02
申请人 MATSUSHITA ELECTRIC IND.CO.,LTD. 发明人 MAZUMODO DOKIGAZU;NAKAGAWAI UKIO;HONZYO MASAHIRO
分类号 H04N5/911;H04N9/64;(IPC1-7):H04N5/92 主分类号 H04N5/911
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