| 摘要 |
PURPOSE: To provide a clock signal regenerating circuit network by comparing a phase of an output signal of a clock signal selection means with a phase of an output signal of a clock latch means and allowing a phase detection circuit to generate an error signal so as to phase-lock an internal clock signal, a data pulse stream and an auxiliary pulse such as a synchronization pulse. CONSTITUTION: A clock phase generator 12 provided to a clock signal generating circuit network that locks a phase of a data signal to an auxiliary and a clock signal generates a multiple phase clock signal whose phase is changed by a predetermined phase from a phase of an original clock signal. A phase clock latch circuit 18 connecting to the generator 12 selects a signal synchronously with the data signal in the multiple clock signal depending on the data signal. Moreover, a phase adjustment circuit 20 shifts a phase of the auxiliary signal in response to the error signal from a phase detector 22, and a clock selection circuit 14 selects a signal in-phase to an output signal of the circuit 20 among the multiple phase clocks. |
