发明名称 REDUNDANT CODE ADDING CIRCUIT SYSTEM OF ELECTRONIC COMPUTER
摘要 PURPOSE:To easily add a parity bit, and to detect a fault of an ROM even during the execution of a processing program, by using a writable and readable volatile storage element in combination. CONSTITUTION:Through an advancing register (li) of a processor 1, an ROM2 and a writable and readable volatile storage element 3 used in combination with it are accessed, and the readout bit data of the ROM2 and its addition value are stored in registers (lg) and (lh). Then, a parity bit is written in the element 3 through the register (lg), a parity generator 6, etc. Since it is not written in the ROM, parity bit addition is faciliated and secured. Further, a parity checker 4 detects a fault of the ROM on the basis of the parity bit in the element 3 even during the execution of a processing program.
申请公布号 JPS57212695(A) 申请公布日期 1982.12.27
申请号 JP19810096953 申请日期 1981.06.23
申请人 KOKUSAI DENKI KK 发明人 KUNII HIROOMI
分类号 G06F11/10;G06F12/16 主分类号 G06F11/10
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