| 摘要 |
PURPOSE: To attain supplying a fixed data pattern when power is supplied by connecting so that each inverter is coupled to individual supply terminals and ground nodes and a memory cell is switched to the prescribed state. CONSTITUTION: A memory cell includes at least one of capacitors 30 or 32 in a low power semiconductor random access memory cell including a pair of cross coupling CMOS inverters 4, 5. Thereby, an output of the inverter 30 being one side of them is coupled to power source voltage Vcc or a ground node, nonsymmetrical electrostatic capacity is given to output of a pair of inverters 4, 5, while a memory cell is forcedly made the prescribed logical state when power is supplied. Thereby, remarkable DC current which exists in a balanced cell and is made to flow when both inverters are conducted during some period can be avoided in the non-symmetrical cell, further, the non- symmetrical memory cell can supply a fixed data pattern at the time of supplying a power source. |
