| 摘要 |
PURPOSE:To make a semiconductor memory of this design both high in integration and low in power consumption by a method wherein a power line electrically connected to the source region of a drive transistor of a flip-flop is formed of a dedicated second conductive layer, and the gate electrode of a load transistor is formed of a dedicated third conductive layer and so on. CONSTITUTION:In a semiconductor memory whose memory cell is composed of a flip-flop formed of a pair of CMOS transistors and a pair of transfer transistors formed of MOS transistors, the electrodes of drive transistors 11 and 12 and transfer transistors 13 and 14 are formed of first conductive layers 51-53 on a semiconductor substrate 50 and a power line 21 electrically connected to the source regions of the drive transistors 11 and 12 is formed of a second conductive layer 54 above the first conductive layers 51-53. The gate electrodes of load transistors 15 and 16 are formed of third conductive layers 56 and 57 above the second conductive layer 54, and the active regions of the load transistors 15 and 16 are formed of fourth conductive layers 61 and 62 above the third conductive layers 56 and 57. |
