发明名称 BUS DATA HOLDING CIRCUIT CONSISTING OF GATE ARRAY DEVICE
摘要 PURPOSE:To realize a bus data holding circuit with the combination of P-type MOSFETs and N-type MOSFETs boith are the same in size by connecting the input/output of a first inversion circuit consisting of the P-type MOSFET and the N-type MOSFET, and a second inversion circuit consisting of plural P-type MOSFETs and N-type MOSFETs. CONSTITUTION:At the bus data holding circuit consisting of a gate array device using an insulation gate field effect transistor(MOSFET), the first inversion circuit 1 consisting of a first P-type MOSFET 11 and a first N-type MOSFET 12, and the second inversion circuit 2 consisting of the P-type MOSFETs 13, 14, and the N-type MOSFETs 15, 16 are provided. And the output of the first inversion circuit 1 is connected to the input of the second inversion circuit 2, and the input of the first inversion circuit 1 to the output of the second inversion circuit 2. In such a way, it is possible to hold bus data even when the P-type MOSFET and the N-type MOSFET same in size are used as in a gate array circuit.
申请公布号 JPH02268510(A) 申请公布日期 1990.11.02
申请号 JP19890091412 申请日期 1989.04.11
申请人 SEIKO EPSON CORP 发明人 TERADA MASAHIKO
分类号 H03K3/356;H03K19/0948;H03K19/173 主分类号 H03K3/356
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