| 摘要 |
PURPOSE:To enable high performance and high integrated circuits to be formed by a method wherein notched parts are formed along the outer peripheral part or inside a wafer and then testing pad parts are mixedly arranged on the other pad pars simultaneously arrayed. CONSTITUTION:The title semiconductor device is provided with a semiconductor substrate 1 having notched parts 15 inside or at least on one side of the outer peripheral part and a plurality of pads 3 formed setting in array on the outer peripheral edge part of the semiconductor substrate 1 and the main surface of the notched parts 15. Furthermore, these pads 3 are provided with bonding pads 3 wired to outer leads 8 and testing pads 3a used for the test of integrated circuits. The notched parts 15 formed on the semiconductor substrate elongate the length of the peripheral edge parts of the semiconductor substrate, thereby increasing the number of pads 3 arrayed along the peripheral edge parts. Through these procedures, the semiconductor device can be composed of high performance logic circuits required of a numerous outer electrodes or logic circuits connected with memory circuits. |
