Distributed cache dram chip.

摘要

A computer distributed cache DRAM is comprised of one or more Dynamic Random Access Memory (DRAM) arrays (22) with sense logic means (24) for storing data outputted from said DRAM arrays (22), a Static Random Access Memory (SRAM) buffer (28) functioning as a Distributed Cache and an on-chip multiplexor (30). A first data bus (26) interconnects the sense logic means (24), the SRAM (28) and the multiplexor (30). A second data bus (32) interconnects the multiplexor (30) and the SRAM (28). A memory controller generates signals which cause information to be extracted from the DRAM arrays (22) while the contents of the SRAM (28) is unchanged or vice versa.