发明名称 Branch instruction control unit based on a pipeline method.
摘要 <p>Disclosed is a branch instruction control unit based on a pipeline method comprising cache memory means(101), branch information means(102), branch address generation means(107), fetch means(100), instruction decode means(108), and instruction executing means(111). In the unit, when the branch instructions are fetched, the branch is predicted in accordance with the branch predictive information in the branch information memory(102). Then, when establishment of the branch is judged, the target addresses are calculated by the branch address generation means 107) before decoding of the branch instructions, and the instructions designated by the target addresses are fetched from the cache memory means(101) to carry out a series of the pipeline processes.</p>
申请公布号 EP0394711(A2) 申请公布日期 1990.10.31
申请号 EP19900106292 申请日期 1990.04.02
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 MIYAMORI, TAKASHI;SASAKI, TOHRU
分类号 G06F9/38 主分类号 G06F9/38
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