| 摘要 |
In the design of a digital adder for two multi-digit binary numbers using majority logic elements, the signal transit times become short if, inter alia, special chips are used. These comprise two majority logic elements M1 and M2 each with three inputs (11, 12 and 13 or 21, 22 and 23). This chip serves to combine two variable pairs y1, xi and yi-1 to form a new variable pair y'i, x'i. A first input (12 or 21) of both majority logic elements M1 and M2 in each case obtains the one higher-order variable yi. The other higher-order variable xi is in each case fed to a second input (13 or 22). The respective third input (11 or 23) receives the one or the other lower-order variable yi-1 or xi-1. The output (14) of the majority logic element M1 yields the variable y'i and the corresponding output (24) of the majority logic element M2 yields the variable x'i as the result of the logic operation. <IMAGE>
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