发明名称 |
Dram with (1/2)VCC precharge and selectively operable limiting circuit |
摘要 |
An amplitude limiting circuit is arranged in a DRAM with (1/2) VCC precharge to equalize an amplitude between a precharge voltage and an "H" level output of each pair of bit lines charged and discharged in an active cycle with an amplitude of the precharge voltage and an "L" level output of each pair of bit lines.
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申请公布号 |
US4967395(A) |
申请公布日期 |
1990.10.30 |
申请号 |
US19890304173 |
申请日期 |
1989.01.31 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
WATANABE, YOHJI;FURUYAMA, TOHRU |
分类号 |
G11C11/409;G11C11/4074;G11C11/4076;G11C11/4094 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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