发明名称 |
Data processor in which external sync signal may be selectively inhibited |
摘要 |
An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is supplied to the external terminal through a control gate while a suitable control signal is inputted to a control terminal of the control gate. According to this circuit construction, control can be made in such a manner that the external sync signal is not supplied to the output terminal in the single-chip mode. As a result, it becomes possible to prevent noise from entering a signal supplied to an adjacent pin through a coupling capacity between the external terminals in the single-chip mode, and to reduce consumed power of an output buffer circuit which is disposed between the control gate and the external terminals.
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申请公布号 |
US4967352(A) |
申请公布日期 |
1990.10.30 |
申请号 |
US19880230047 |
申请日期 |
1988.08.09 |
申请人 |
HITACHI, LTD.;HITACHI MICROCOMPUTER ENGINEERING LTD. |
发明人 |
KEIDA, HARUO;TSUKAMOTO, TAKASHI;NAGASAKI, NOBUTAKA |
分类号 |
G06F15/78;G06F1/10 |
主分类号 |
G06F15/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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