| 摘要 |
PURPOSE:To reduce the size of a chip by forming an impurity diffusion layer having a conductivity type reverse to a substrate to the lower section of the lifting contact section of a word line and connecting the impurity diffusion layer to the word line in the lower section of the lifting contact section. CONSTITUTION:An N<+> diffusion impurity layer 2 is concentrated and formed onto the surface of the semiconductor substrate 9 (P-type) of contact sections between a cell section and a cell section to which the word contact sections 1 (the lifting contact sections of word lines) of polysilicon layers 6 extending to the left and the right as the word lines functioning as the gates of memory cell transistors in combination and aluminum layers 5 overlapped to the upper sections of the layers 6 are concentrated and shaped. Each impurity layer 2 is arranged to sections just under the word-line lifting contact sections 1, capacitive polysilicon layers 7 are cut 8, and the polysilicon layers 6 are connected to the N<+> impurity layer 2 in sections just under the lifting contact sections 1. Accordingly, the area of a chip is reduced. |
