EEPROM system with bit error detecting function

摘要

An EEPROM system with an error detecting function comprising: a memory cell matrix (10) composed of a plurality of MOS memory cells (D0 through D3) and a plurality of bit lines (11) connected separately to the plurality of the MOS memory cells (D0 through D3); and a plurality of intermediate state detecting circuit (31) connected separately to the plurality of the bit lines (11) for detecting an intermediate state other than writing and erasing states of the MOS memory cells (D0 through D3), and for outputting an error bit indicating signal, the intermediate state being a threshold voltage between a threshold voltage of a storage MOS memory cell (Q2) in a writing state included in each of the MOS memory cells (D0 through D3) and a threshold voltage of the storage MOS memory cell (Q2) in an erasing state.