| 摘要 |
A system and method is disclosed for generating a synthetic netlist which mimics the size and complexity of a specified target circuit. The first step of synthetic netlist generation is to generate an abstract of the netlist of a known circuit of the same type as the specified target circuit. Information in the abstract specifies the relative usage rates of the circuit elements in the known circuit and the complexity of the interconnections between circuit elements and circuit signals. The second step is to generate a synthetic netlist, scaled to include a specified number of circuit elements. The circuit elements in the synthetic netlist are interconnected in a sequential process so as to have the interconnection complexity specified by the abstract of the known circuit. While the circuit represented by the resulting synthetic netlist would not perform any useful circuit function, the layout of the synthetic netlist will accurately represent the size and interconnection complexity of the specified target circuit. The synthetic netlist generated by the present invention is suitable for use with a silicon complier so as to generate a circuit layout representative of the specified target circuit.
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