发明名称 METHOD FOR TESTING LOGICAL CIRCUIT
摘要 PURPOSE:To evaluate the quality of a test pattern without using a trouble model by performing functional/logical simulation with respect to circuit data of a function/gate level subjected to bit range division to calculate a function activating rate. CONSTITUTION:Function/gate level circuit data 11a, 11b are divided into a predetermined number or less of bit ranges by a bit range dividing means 12 and, on the basis of the results of functional/logical simulations 13a, 13b, function activating rates are calculated at every divided bit ranges by a function activating rate calculation means 14 according to a predetermined calculation method. A test pattern 16 is evaluated using a set 15 of function activating rates such as the calculated one-bit activating rate, two-bit activating rate, a three-bit activating rate or the like. By this method, the quality of the test pattern can be evaluated without using a trouble model to obtain a method suitable for an IC for a specific user.
申请公布号 JPH02262076(A) 申请公布日期 1990.10.24
申请号 JP19890083586 申请日期 1989.03.31
申请人 TOSHIBA CORP 发明人 HIRABAYASHI KANJI
分类号 G01R31/317;G06F11/22;G06F17/50 主分类号 G01R31/317
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