| 摘要 |
PURPOSE:To increase pulse width of decoder output by generating a reset signal while inputting output of a decoder that decodes the content of a divider and a clock signal. CONSTITUTION:A clock signal CP of output of an oscillator is inputted to a frequency dividing circuit 1 and when the content of the frequency dividing circuit obtains a specified state, output Pgamma is outputted from a decoder 3. Logical product of the output Pgamma and clock signal CP is obtained in a gate 4 resulting to be a reset signal of the frequency dividing signal 1. Since the reset signal is not applied after rising of Pgamma until next clock signal CP rises in succession to Pgamma rising, pulse width of Pgamma obtains sufficiently large. |
