发明名称 DATA PROCESSOR
摘要 <p>PURPOSE:To shorten the exclusive time of a bus according to initialization by making access to a memory by specific addresses simultaneously, and performing the initialization of banks in the memory simultaneously. CONSTITUTION:The data processor is constituted of a main memory device 2 and a system controller 1 which starts up the initialization of the memory by controlling a common bus 3. When the initialization of the memory is recognized at the main memory device 2, a bank select line 23 is enabled for each bank 22 by an address conversion circuit 21, and the same address (a) is supplied, and write data (all '0's) are written simultaneously on plural banks 22. Therefore, it is possible to shorten the exclusive time of the bus by the initialization of the memory, and to suppress influence on work using another bus when the system is started up. In such a way, start-up time can be accelerated.</p>
申请公布号 JPH02259814(A) 申请公布日期 1990.10.22
申请号 JP19890080604 申请日期 1989.03.30
申请人 NEC CORP 发明人 HASEGAWA YASUSHI
分类号 G06F1/24;G06F12/02;G06F12/06 主分类号 G06F1/24
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