| 摘要 |
PURPOSE:To prevent an equivalent resistance from being decreased and a distortion factor from being deteriorated, by adding a simultaneous high-level eliminating circuit which prevents a forward and a reverse clock signal from going to high level at the same time. CONSTITUTION:A clock signal is inputted to one input terminal of a two-input AND gate 16 of the simultaneous high-level eliminating circuit 15 from a clock oscillating section 14 and the other input terminal is connected to a power supply 13. Thus the input and output characteristic of the gate 16 has a threshold voltage VTH. On the other hand, the two input terminals of a two-input NAND are connected to the oscillating section 14, its input and output characteristic has the threshold voltage VTH', which is formed slightly higher than the voltage VTH. Further, an output of the gate 16 is connected to an inverter circuit 18. Thus, signals which do not go to a high level at the same time are obtained in output clock signals phi1 and -phi1 of the circuit 15. |
