发明名称 FUGOKAKAIRO
摘要 PURPOSE:To simplify the configuration of an encoder having priority in an associative memory by resetting input side nodes on respective stages corresponding to priority by a switch circuit and impressing a transmission control input to the succeeding step in accordance with an output. CONSTITUTION:A switch S1 is controlled by a clock C1 and a node Q is changed in accordance with its input, an when an input iN is ''1'' and a transmission control input P1 impressed to a switch S6 and an AND circuit A is ''1'', the output OUT is ''1''. Switches S2, S3 are controlled by a clock C2 synchronized with the clock C1 and its inversion clock C3, the node Q is reset to ''0'' in accordance with the ouput OUT and the reset state is not released by the holding function of the switch S2 until the node Q is set by the switch S1. On the other hand, a switch S5 connected to the earth and the switch S6 to which the signal P1 is impressed are actuated in accordance with the state of the contact Q, and only when the input iN is ''0'' and the resetting has been completed, a transmission control input P2 to the succeeding stage is made ''1''. Thus, the input can be encoded without intermediate encoding and the configuration of the encoder with priority is simplified.
申请公布号 JPH0247038(B2) 申请公布日期 1990.10.18
申请号 JP19830168601 申请日期 1983.09.13
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NISHIMICHI YOSHIHITO;KADOTA HIROSHI
分类号 H03M7/00;G11C15/04 主分类号 H03M7/00
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