| 摘要 |
<p>PURPOSE:To improve a data holding time and a data reloading time by preventing a voltage from being impressed excepting a time, in which information area read, in the control gate and drain of a memory cell. CONSTITUTION:A control gate voltage VCG is lowered to zero volt and a voltage VBL of bit lines BL1-BLn is lowered to zero volt, afterwards, a word line WL1 is turned off, in other words, a voltage VWL1 of the word line WL1 is lowered to zero volt. By the dynamic reading timing, a charge accumulated in the control gate of memory transistors 11-14 can be discharged and the voltage is not impressed to the memory transistors 11-14 excepting the time of data reading. All word lines WL are turned off in a standby mode and the voltage is not impressed to the drain and control gate. Thus, the time to impress a bias to the control gate can be shortened and the data holding time and data reloading time can be improved.</p> |
