| 摘要 |
<p>A fractional-N synthesiser including a phase locked loop comprising: a voltage controlled oscillator (4) providing a loop output signal, the output signal being coupled via an N variable divider (6) to a first input of a phase or frequency detector (8); a reference frequency source coupled to a second input of the phase or frequency detector (8), the detector providing at an ouput a control signal, in dependence upon a comparison between the signals applied to the first and second inputs, for application to a control input of the voltage controlled oscillator (4); and means for setting the division ratio (N) of the variable divider (6) in response to a frequency data word, including interpolator means (50) for periodically varying at least the LSB of the frequency data word, the interpolator means (50) comprising an input for receiving said LSB, a combiner means (70, 80) for comparing the LSB with a feedback signal, and a quantiser circuit (72, 84) and a filter circuit (74, 82) providing a predetermined delay or integration function, such circuits being coupled to said combiner means (70, 80) for providing said feedback signal and a ratio setting signal to the variable divider (6).</p> |
