发明名称 HOLDING TYPE REGISTER ACCESS SYSTEM
摘要 PURPOSE:To extract repeatedly data by providing a tri-state buffer and specifying a single address through a data receiving bus. CONSTITUTION:One-word data d1-dn from a data transmitting bus 1 are transmitted to holding type registers 5-1-5-n together with respective fed addresses a1-an and n-word data d1-dn are stored in the registers 5-1-5-n. In this state, when only one kind of address (a) and a data extraction indication supplied from the data receiving bus 2 to the registers 5-1-5-n in common are sent out once, an access signal C drives the counting circuit CNT in a control part 6 once to output logic 1 from a terminal Q0 and logic 0 from terminals Q1-Qm. Consequently, a decoder DCR outputs an enable signal en1 from a terminal 01 to energize a tri- state buffer 7-1. Then, the register 5-1 is connected to the data receiving bus 2 to allow the stored data d1 to be extracted. Similarly, data are extracted successively up to the holding type register 5-n.
申请公布号 JPS59231647(A) 申请公布日期 1984.12.26
申请号 JP19830107138 申请日期 1983.06.15
申请人 FUJITSU KK 发明人 HASHIMOTO SHIYUUICHI
分类号 G06F5/06;G06F13/38;G06F13/40;(IPC1-7):G06F5/06 主分类号 G06F5/06
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