System providing cache coherent direct memory access between dissimilar bus systems.

摘要

An interface circuit permits a first bus master connected to a first bus to directly access a main memory connected to a second bus while maintaining coherency between corresponding data in the main memory and a cache memory used by a second bus master on the second bus. The interface circuit maps selected first bus addresses to corresponding second bus addresses such that when a bus master on the first bus attempts to read or write access one of the mapped first bus addresses, the bus interface circuit responds by read or write accessing a corresponding address in the memory on the second bus. The bus interface circuit stores SNOOP data indicating which memory addresses contain data cached in the cache memory, and when accessing a cached memory address, the bus interface circuit places a signal on the second bus telling the second bus master to copy data from the cache memory into the main memory before the interface circuit performs a main memory read access or to copy data from the main memory to the cache memory after the interface circuit completes a main memory write access, thereby to maintain coherency between the main memory and the cache memory.