High speed asynchronous data interface.

摘要

A digital data interface for high speed asynchronous data transfer is described. The design is nominally intended for integration onto the component chips in communications systems. The system is described with respect to its realisation in CMOS IC technology. The techniques involved, however, may easily be applied to other technologies. The interface employs Manchester Bi-Phase Mark encoding of the clock and data to allow extraction of the clock and data signals at the receiver (7). Furthermore, use of this Manchester code allows code violations to be easily employed as frame markers for synchronisation means. The essence of the clock extraction and data detection circuit (9, 11) is the use of calibrated delay line elements to suppress data transitions within the coded input signal, thus allowing the clock transitions to be detected from which the clock is then generated.