| 摘要 |
A programmable delay generator is based upon an asynchronous or ripple counter the stages of which change state at definably different times. A full terminal count is decoded stage which changes state at a unique time which is different from the time at which any other stage changes, for thereby defining an unambiguous delay period. A partial terminal count programmably determines the length of circuit output and the reloading of the ripple counter with a programmable, time delay determining, initial value. |
