| 摘要 |
A method for screening EPROM-related integrated circuits for endurance failure is described. The screening method is based on a measurement of the number and distribution of cells within the EPROM-related device which program and/or erase significantly further and faster than "normal" cells. The erase speed of the floating gate cells are first measured to obtain an erase distribution for the IC in which the percentage of bits erased is plotted as a function of the applied gate threshold voltage. The number of bits which are located in the erase tail region of the distribution is then identified. If this number exceeds a certain percentage of the total bits in the array the IC is classified as one which is likely to suffer early endurance failure. Compared to traditional cycling screens, the method of the present invention identifies unreliable material non-destructively and does not require extra floating-gate cells or error-correction logic overhead. |
