APPARATUS AND METHOD FOR ADDRESSING SEMICONDUCTOR ARRAYS IN A MAIN MEMORY UNIT ON CONSECUTIVE CLOCK CYCLES

摘要

Apparatus is disclosed for selecting a group of address signals to be applied to a memory unit array and for applying the address signals to the memory unit array to permit the activity associated with the address signals to be completed. The apparatus generates a multiplicity of signals controlling a latchtype buffer storage unit. The first generated signal insures that the signal controlling the buffer storage unit is active during application of the address signals to the system bus. The second generated signal overlaps the first generated signal and extends the signal controlling the buffer storage unit a small amount. The third generated signal overlaps the second generated signal and extends the signal controlling the buffer storage unit for the period of time necessary to utilize the memory unit array.