| 摘要 |
PURPOSE: To attain holding a reference of a system constant by controlling the number of elements of a load being active during a reading operation period and a margining period and supplying margining voltage to a memory cell. CONSTITUTION: Plural load elements 22 are coupled between high voltage and a node in parallel, each switching transistor 24 is coupled to corresponding load elements 22 in series, and each loads 22 are activated. CMOS technology is used for a circuit 20, and each load 22 of the circuit 20 is constituted with (p) channel transistors. Gates of each transistor 24 are driven by an individual line 23, corresponding transistor 24 is activated by making a given line 23 a low level signal state, and a load 22 corresponding to it is inserted to a circuit between VCC and a node 12a. A rate of load depends on the number of incorporated transistors 22. In this case a reference current IREF is constant in the circuit 20, thereby, more stable and continuous reference value can be obtained. |
