发明名称 JIKANSUITSUCHI
摘要 PURPOSE:To improve the flexibility to traffic variance by adding the function of extension of bit width in a holding memory and the function of selective write in bit units of a channel memory in a time division switch of a time division exchange or the like. CONSTITUTION:An incoming highway 201 is a 1,024kb/s highway where time slots TS0-TS15 are multiplexed at 8kHz period, and data is shifted by a time corresponding to one time slot and is set to a register 11 in parallel by a clock 203. The write mode of data is stored in a holding memory 16 in accordance with the time slots, and a counter 15 transmits a counted value synchronized with a time slot number to determine a read address of the memory 16. The read result is designated as a write address of a memory 12. Contents of the memory 12 are read out sequentially in accordance with an output 214 of the counter 15 and are set to a register 14 at the timing of a clock 210.
申请公布号 JPH0245879(B2) 申请公布日期 1990.10.12
申请号 JP19830090030 申请日期 1983.05.24
申请人 HITACHI LTD 发明人 TAKEMURA TETSUO;GOHARA SHINOBU
分类号 H04Q3/52;H04Q11/04;H04Q11/06 主分类号 H04Q3/52
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