发明名称 TIMER CHANNEL FOR USE IN PLURAL CHANNEL TIMER SYSTEMS
摘要 <p>PURPOSE: To reduce the load of a CPU by controlling plural channel timers, in which individual channels independently executes functions for a fixed time, by means of a private single purpose processor so as to improve a timer used for plural channel timer system. CONSTITUTION: When an MTSRE control signal from a service processor is active, it becomes possible to generate a transition detecting service request signal and a matching recognition request signal. Until the state of the MTSRE signal at each channel is latched and the state of MTSRE changes, the state is kept. Then when a pin 140 detects transition, a transition detecting latch 145 is set and an acquiring event 148 triggers the loading of an acquiring register 131 by the value of a selected TCR bus to consecutively acquire one state. Thereby the interposing of the CPU is reduced to reduce its load.</p>
申请公布号 JPH02252009(A) 申请公布日期 1990.10.09
申请号 JP19890210829 申请日期 1989.08.17
申请人 MOTOROLA INC 发明人 ROBAATO ESU POOTAA;BAANON BII GOORAA;GEIRII ERU MIRAA;SUTANREI IIGUROUBUSU;MARIO NEMIROBUSUKII
分类号 G06F1/14 主分类号 G06F1/14
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