DATA OUTPUTTING BUFFER FOR STATIC RAM USING HIGH IMPEDANCE

摘要

The data output buffer comprises a first NOR circuit (41) for receiving a positive output (SAS) of the differential amplifier (SA) and an output enable signal (OE) of the read/write control buffer (R/ WB); a second NOR circuit (42) for receiving the negative output (SAS) of the amplifier (SA); a common ground connecting means (43) commonly connected between a ground of the circuit (41) and a ground of the circuit (42); an inverting circuit (44) receiving an output signal of the circuit (41); a set form circuit (45) receiving an output signal of the circuit (42); and a data output circuit (46) having transistors (T16)(T17).