| 摘要 |
<p>As shown in Figure 2, a phase detector comprises a digital phase detector circuit having an up/down counter (6) for counting clock pulses (CPS) to determine the number of clock pulses that occur in the time interval between the centre of opposite edges of a first signal (VCS) and one edge of a reference signal (PL) synchronised with the clock pulses (CPS). A latch (7) provides a first digital output signal (DES) which represents said number. The phase detector also has an analogue phase detector circuit having a flip-flop (13) for producing a second signal (VCS') which corresponds to said first signal (VCS) and is synchronised with said clock pulses (CPS). Logic gates (9) and (10) determine the time intervals between corresponding edges of said first and second signals (VCS,VCS min ), and a circuit element (8) determines a phase error voltage (VS) from these time intervals. Means (12) digitise said voltage (VS) to provide a second digital output signal (AES). The first and second digital output signals (DES,AES) are combined to produce a resultant digital output signal (DPE) which represents an overall indication of phase difference.</p> |
