| 摘要 |
<p>PURPOSE:To prevent the occurrence of duplicate read of a data or a defect due to a phase jitter or the like in the succeeding operation by selecting suitably a frame timing at the write side and the readout side of an elastic store at the start of a system. CONSTITUTION:A selector 5 is provided with respect to an n-clock delay element 1, a selector 2, an elastic store 3 and an AND circuit 4 in a frame aligner to set variably the approach inhibiting range M in the frame timing at the write and readout sides of the elastic store 3. Moreover, either the inhibiting range M of the selector 5 which is within m1 clocks or that of within m2 clocks is selected. The relation of m2 clock < m1 clock is selected under the condition with the maximum value delta of phase jitter, the selector 5 selects the m1 clock an input terminal theta1 at the input of a system reset RST and then selects the m2 clock at the side of an input terminal theta2 to make the operation of the elastic store 3 stable.</p> |
