| 摘要 |
PURPOSE:To shorten the pull-in setting time by allowing plural frame synchronization deciding circuits to simultaneously apply the synchronizing decision of each bit data constituting one short-frame. CONSTITUTION:A clock generating circuit 22 generates N phases of clocks whose bit number is the same as a bit number N constituting a short-frame and whose phase differs by one bit period. Moreover, frame synchronization deciding circuits 231-23N compare a synchronous signal generated from an input digital signal with the input digital signal to apply the frame synchronization decision. That is, the N-phase clock generated by the clock generating circuit 22 is inputted separately to the frame synchronization deciding circuits 231-23N and the synchronous signal pattern generated in each circuit is generated based on the input data of the time slots deviated by one bit each in the input digital signal. Thus, the synchronization decision by one short frame is implemented simultaneously and the pull-in setting time is shortened. |
