发明名称 RATSUCHIATSUPUBOSHIKAIRO
摘要 PURPOSE:To reduce a surge current entered from the outside to cause the trigger of latching up by a method wherein an LSI to be provided on a substrate is constructed of a diode formed between both the terminals VDD, VSS of an electric power source, and a resistor and an MOS transistor connected in diode connection, and a voltage between both the terminals of the MOS transistor is supplied to the inside circuit of the LSI. CONSTITUTION:A P<+>N<->N<+> diode 22 and a resistor component 23 provided to an N<-> type substrate are connected in series between a VSS terminal 20 and a VDD terminal 21, and moreover a series body 40 built in with a resistor 24 and an N-channel MOS transistor short-circuited with the gate, the source and the P<-> well is connected in parallel with the circuit thereof. After then, the terminals 26, 27 of the series body 40 are connected to the inside circuit of the LSI. Accordingly, when a surge current is applied between the terminals VSS, VDD, the surge current is absorbed by the series body 40 to reduce an influence to the inside circuit, and a counterplan in regard to latching up in the inside circuit is made unnecessarily.
申请公布号 JPH0244153(B2) 申请公布日期 1990.10.02
申请号 JP19830031186 申请日期 1983.02.24
申请人 MITSUBISHI ELECTRIC CORP 发明人 KUBO HIROSHI
分类号 H01L27/08;H01L27/092;H01L29/78 主分类号 H01L27/08
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