发明名称 SELECTIVE PROJECTION LIMITING METHOD SNITABLE FOR USE IN MANUFACTURING OF FLOATING GATE TRANSISTOR
摘要 PURPOSE: To facilitate assembling of floating gate FETs for double control gate programmable element by oxidation according to a method wherein a first patterning layer of a non-monocrystal positive conductive material is made on an upper surface of a lower structure, and a projection in which an upper lateral edge of the remaining of the first patterning layer projects outwardly is formed. CONSTITUTION: A first patterning layer 16 of an n type non-monocrystal type silicon is deposited on a lower structure formed by a substrate 10, a field region 12 and a dielectric layer 14. Later, a patterning monosilicon layer 16 being a floating gate is present in part of the dielectric layer 14 and ranges over a portion adjacent to the field region 12. Since a main electric insulation layer 22 of silicon dioxide is grown along an upper or lateral surface of the patterning layer 16, low temperature oxidation is conducted. As the oxidation is conducted at a temperature within a range of 800 to 950 deg.C, the entire upper lateral edge of the remaining 16A of the layer 16 forms a pointed projection 24 projecting upward and laterally outward.
申请公布号 JPH02246164(A) 申请公布日期 1990.10.01
申请号 JP19890320358 申请日期 1989.12.08
申请人 PHILIPS GLOEILAMPENFAB:NV 发明人 TEE I JIEIMUZU CHIEN
分类号 G11C16/04;H01L21/28;H01L21/336;H01L21/8247;H01L27/115;H01L29/788;H01L29/792 主分类号 G11C16/04
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