| 摘要 |
PURPOSE: To realize a high speed processing by providing a means for delaying a parameter, a means for designating an address in reverse bit order and a means for rounding up a fixed result. CONSTITUTION: The multiplexer of a first output part selectively connects a signal which an arithmetic and logic unit 240, or the multiplexer of a funnel shifter 300/merge logic device 302 generates, to plural output part registers. The multiplexer of a second output part selectively connects a signal which the plural output registers generate or a signal generated on a 'YO' 462 bus, to an 'FB' bus 190a. The multiplexer of a third output part selectively connects a signal which the 'F1' and 'F2' registers 404 and 406 of the output part or the first output part multiplexer generates, to a bit inverse transfer device 481, a rounding device 422 and a shifter 462. The multiplexer of a fourth output part selectively connects a bit inverse transfer device 418, the rounding device 422, the shifter 426 or the third output part multiplexer to an output driving device 433 generating the signal to the 'YO' bus 462. Thus, the high speed processing is executed. |
