| 摘要 |
PURPOSE:To realize fast processing by processing the transfer of data and commands, the execution of a transfer instruction and an arithmetic instruction, and the execution of the arithmetic instruction and arithmetic instruction in parallel. CONSTITUTION:A primary instruction execution part 10 which processes the transfer instruction and plural secondary instruction execution parts 12-1-12-n which process the arithmetic instruction are provided and instruction execution information which enables the secondary instruction execution parts 12-1-12-n to operate in parallel is stored in a data register file 14. Then selectors 16 and 18 takes the instruction execution information out of the data register file 14 and distributes it to the secondary instruction execution parts 12-1-12-n and at the same time, other selectors 20 and 22 take execution results after processing out of the secondary instruction execution parts 12-1-12-n and stores them in the data register file 14. Routers 24-1-24-n are provided at the output stages of the secondary instruction execution parts 12-1-12-n to enable variable- length pipeline operation. Consequently, the fast arithmetic becomes possible. |
